fujitsu semiconductor data sheet copyright?2012 fujitsu semiconductor limited all rights reserved 2012.10 semicustom cmos standard cell CS401 series description the CS401 series of 28 nm standard cells is a line of cmos asics that satisfy demands for lower power consumption, higher spe ed and higher integration. these cells offer the minimum level of leakage current in the semiconductor industry, and are able to imple- ment a mixture of core transistors with four differen t threshold voltages, as appr opriate for the applications ranging from handheld terminals to digital audiovisual equipment. the integration level in this series is twice the cs302 series with lower power consumption and higher speed. features ? technology : 28 nm metal-gate cmos : maximum 11-metal layers. ultra low permitt ivity material is used for dielectric inter-layers. : four different types of core transistors (low leak, standard, high speed and ultra high speed) can be used on the same chip. ? supply voltage : internal power supply : + 1.0 v 0.1 v : external power supply : + 1.8 v 0.15 v (1.8v interface on dual-power supply system) + 2.5 v 0.2 v (2.5v interface on dual-power supply system) + 3.3 v 0.3 v (3.3v interface on dual-power supply system) ? junction temperature range: ? 40 c to + 125 c (standard specification) ? gate power consumption: 0.61 nw / gate (operatin g condition: 1.0 v, operating rate 0.5, 1 mhz) ? support high-quality, various types of cell sets de veloped by fujitsu semiconductor (from low power versions to high speed versions). ? support srams with standby-mode and power-dow n mode for lower power consumption memories. ? compiled cells (ram, rom, others) ? support special interfaces (lvds, sstl, others). ? support boundary scan test. ? support use of industry standard libraries. ? support use of industry standard tools. ? short-term development using a physical prototyping tool ? one pass design using a physical synthesis tool ? hierarchical design environment for supporting large-scale circuits ? support signal integrity, emi noise reduction. (continued) ds601-00001-2v0-e
CS401 series 2 ds601-00001-2v0-e (continued) ? support static timing sign-off. ? improve timing convergence by using stat istical static timing analysis (ssta). ? design for manufacturing (dfm) enables stab le product-supply and reduced variation. ? package lineup: fbga, pbga, tebga, fc-bga note: including items under development. macro libraries (including macros currently being prepared) 1. logic cells (about 400 types) library sets having four different threshold voltages of core transistors. ? adder ? and ? and-or ?and-or inverter ? buffer ? clock-buffer ? delay buffer ? enor ? eor ?inverter ? latch ? nand ?nor ? or ? or-and ? or-and inverter ? scan flip flop ? non-scan flip flop ? selector ? others 2. ip macros *: arm, arm7tdmi-s, arm946e-s, arm926ej-s, arm1176jzf-s, cortex-m3, coretex-r4f and cortex-a9 are the trademarks of arm li mited in the eu and other countries. 3. special i/o interface macro cpu/dsp arm tm * cores (arm7tdmi-s tm *, arm946e-s tm *, arm926ej-s tm *, arm1176jzf-s tm *, cortex-m3 tm *, cortex-r4f tm *, cortex-a9 tm * mpcore), peripherals ip mixed signal macro adc, dac, opamp, others compiled macro sram (1 port, 2 port), rom, product sum calculator, others pll analog pll special i/o lvds, sstl18, pci, i 2 c interface macro usb2.0 device/host, seri al-ata, pci-express, ddr2, hdmi, others
CS401 series ds601-00001-2v0-e 3 compiled cell compiled cells are macro cells that can be automatically generated by specifying the bit/word configuration. the following compiled cells are available for the CS401 series. ? memory capacity name category memory capacity (bit) clock synchronous single-port ram (1rw) high-density 64 to 1152 k high-speed 32 to 80 k large-scale 16 k to 9 m clock synchronous dual port ram (2rw) high-density 32 to 144 k clock synchronous rom ? 128 to 1152 k clock synchronous register file (1rw) ? 80 to 36 k clock synchronous register file (1r1w) ? 32 to 72 k clock synchronous register file (2r2w) ? 16 to 18 k
CS401 series 4 ds601-00001-2v0-e absolute maximum ratings *1: v ss = 0 v *2: internal gates *3: 1.8 v interface on dual-power supply system *4: 2.5 v interface on dual-power supply system *5: 3.3 v interface on dual-power supply system *6: the output current varies depending on the number of wi ring layers in the chip and the wiring configuration of the i/o cells. contact the sales representative for details. *7: for details about the power supply pin cu rrent, contact the sales representative. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage* 1 v dd ? 0.4 + 1.4 v *2 ? 0.5 + 2.5 *3 ? 0.5 + 3.6 *4 ? 0.5 + 4.6 *5 input voltage* 1 vi ? 0.5 v dd + 0.5 ( 2.5 v) v *3 ? 0.5 v dd + 0.5 ( 3.6 v) *4 ? 0.5 v dd + 0.5 ( 4.6 v) *5 output voltage* 1 vo ? 0.5 v dd + 0.5 ( 2.5 v) v *3 ? 0.5 v dd + 0.5 ( 3.6 v) *4 ? 0.5 v dd + 0.5 ( 4.6 v) *5 storage temperature t stg ? 55 + 125 c operation junction temperature tj ? 40 + 125 c output current* 6 io ?? ma power supply pin current* 7 id ?? ma
CS401 series 6 ds601-00001-2v0-e memo
CS401 series ds601-00001-2v0-e 7 memo
CS401 series fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 902 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ fujitsu semiconductor shanghai co., ltd. 30f, kerry parkside, 1155 fang dian road, pudong district, shanghai 201204, china tel : +86-21-6146-3688 fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ fujitsu semiconductor pacific asia ltd. 2/f, green 18 building, hong kong science park, shatin, n.t., hong kong tel : +852-2736-3232 fax : +852-2314-4207 http://cn.fujitsu.com/fsp/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such informa tion. when you develop equipment incorporat ing the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent ri ght or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconductor assumes no liab ility for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any thir d party for any claims or damages aris- ing in connection with above-mentioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department
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